MSIR.1096
MSIR.1096 DFLTCC hardware compression enabled
During initialization of the compression subsystem, Model 204 determined that the hardware DEFLATE Conversion Facility (the DFLTCC instruction) is available on this processor, and has enabled it. Deflate compression and inflate decompression will be performed by the hardware instruction instead of by the equivalent software routines, which substantially reduces the CPU cost of compression.
The facility is detected at initialization by testing facility bit 151 of the stored facility list; it is available on IBM z15 and later processors. When it is present, Model 204 allocates the parameter block and history buffer that the instruction requires for each compression buffer.
Response: None required. The message is informational and is issued once, at initialization, to the operator and the audit trail. Compare with MSIR.1097, which is issued when the facility is not available.
Message attributes:
| RETCODEO=0 | Sets online return code |
|---|---|
| RETCODEB=0 | Sets batch (single user) return code |
| CLASS=I | Information class; the message can be suppressed with the X'02' bit setting of the MSGCTL parameter |
| AUDITMS | Writes the message with line type MS to the audit trail |
| NOCOUNT | Does not increment the error count (ERCNT) parameter |
| OPR | Writes the message to the (operator) console |